When a semiconductor device including a MOS transistor comprises a constant-voltage generating circuit, a AD/DA converting circuit or the like that includes a feedback function such as voltage detection, a resistance element is needed. For such a resistance element, a high resistivity to reduce a potential variation caused by current flowing through the resistance element is necessary and further it is desirable that an error in resistivity due to a fluctuation in fabrication process be reduced. For example, a resistivity of about 1M.OMEGA. to 10M.OMEGA. is required. In a semiconductor device (including a MOS transistor) using a 0.2 .mu.m design rule, conductive film used as a wiring material is likely to have a lowered resistivity, and the transistor gate electrode is of metal polycide film layered on N.sup.+ -type polysilicon film, and other lower wiring is of metal silicide film. For example, in a semiconductor device including DRAM with stacked type memory cells, a material composing cell plate electrodes has changed from N-type polysilicon film into a laminated film of, e.g., titanium nitride (TiN) film and tungsten silicide WSi.sub.2 film, with employing a high-inductivity film of, e.g., tantalum oxide (Ta.sub.2 O.sub.5), although its main object is not to lower the resistivity.
As a material to compose the resistance element, a second N.sup.+ -type polysilicon film formed on the surface of field insulating film is, in general, preferable. In this case, even when a semiconductor component such as a MOS transistor is formed using the 0.2 .mu.m design rule, the resistance element is typically formed to have a line width of about 0.8 .mu.m to reduce an error in resistivity due to a fluctuation in the fabrication process.
In a semiconductor device including DRAM with stacked type memory cells, to effectively reduce the aspect ratio of a bit contact hole, a node contact hole etc., an extraction pad that is directly connected to a N-type source/drain region of a MOS transistor to compose a memory cell which self-aligns to an insulating film spacer formed on the side of a word line and is connected to a bit line or a storage node electrode is provided. The extraction pad is of a second N.sup.+ -type polysilicon film, therefore the resistance element can be also formed of the second N.sup.+ -type polysilicon film. Even when such a semiconductor device including DRAM is formed using the 0.2 .mu.m design rule, the resistance element needs to be formed to have a line width of about 0.8 .mu.m. The thickness of the second N.sup.+ -type polysilicon film of the semiconductor device is 0.15 .mu.m (150 nm) on the surface of field insulating film, but a quite thick part in the cell array region occurs since a part with no word line is filled therewith. Therefore, when the resistance element and the extraction pad are formed by using the same second N.sup.+ -type polysilicon film in a photolithography process, over-etching is required because the etching time for the second N.sup.+ -type polysilicon film of 150 nm thick cannot be used as a standard. Due to the need to avoid the overetching required to provide the resistance element with a line width of 0.2 .mu.m, the line width of the resistance element needs to be about 0.8 .mu.m.
Thus, in a typical semiconductor device or a semiconductor device including DRAM, the resistance element must have a quite large occupied area. For example, when a resistance element with a resistivity of 5M.OMEGA. is formed by using a second N.sup.+ -type polysilicon film with a thickness of about 150 nm and a layer resistance of 50.OMEGA./.quadrature., the occupied area is as follows: For example, when the resistance element with a line width of 0.8 .mu.m is formed repeatedly turning around in a certain direction with an interval of, e.g., 0.8 .mu.m, the occupied area necessary for this resistance element is about 128.times.1000 .mu.m.sup.2.
Meanwhile, in a semiconductor device including a MOS transistor, another element with a large occupied area other than the resistance element may exist. Namely, when such a semiconductor device includes a constant-voltage generating circuit, the constant-voltage generating circuit needs to have a capacitance element with a large capacitance, such as a pumping capacitor and a compensating capacitor. The capacitance value of such a capacitance element is about 10.sup.3 to 10.sup.5 pF. Such a capacitance element is composed by, for example, connecting in parallel several N-channel MOS transistors with a gate length L/gate width W of 50 .mu.m/50 .mu.m, thereby having a N-type source region, a N-type drain region and a channel region (in an inverted state) in the N-channel MOS transistor as one electrode, and a gate electrode as an opposed electrode. For example, in the case of a compensating capacitance element of 3000 pF, the occupied area is 100.times.6100 .mu.m.sup.2, provided that the gate oxide film in the N-channel MOS transistor is 7 nm thick.